1. Field of the Invention
The present invention relates to liquid crystal displays, and more particularly to line-on-glass (LOG)-type liquid crystal displays capable of compensating for signal voltage differences between gate driver integrated circuits due to intrinsic line resistances of LOG-type patterns on liquid crystal display panels.
2. Description of the Related Art
Generally, liquid crystal displays (LCDs) use an electric field to control light transmittance characteristics of liquid crystal material. Accordingly, LCDs typically include a liquid crystal display panel having a plurality of liquid crystal cells arranged in a matrix pattern and a driving circuit for driving the liquid crystal cells to display a picture on the liquid crystal display panel.
The liquid crystal cells are arranged on the liquid crystal display panel at locations where gate lines are found to cross data lines. Electric fields may be applied to the liquid crystal material by pixel and common electrodes arranged in the liquid crystal display panel. Each pixel electrode is connected to any one of data lines via source and drain electrodes of switching devices such as thin film transistors. Gate electrodes of each thin film transistor are connected to corresponding gate lines, thereby allowing pixel voltage signals to be applied to each of the pixel electrodes of each gate line.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate and data drivers, and a power supply for supplying driving voltages used in driving the LCD. The timing controller controls the gate and data drivers by controlling a driving timing of the gate and data drivers and applying pixel data signals to the data driver. Driving voltages generated by the power supply include common (Vcom), gate high (Vgh), gate low (Vgl) voltages, etc. The gate driver sequentially applies scanning signals to the gate lines, thereby sequentially driving the liquid crystal cells on the liquid crystal display panel one gate line at a time. The data driver applies data voltage signals to each of the data lines whenever a gate line receives a gate signal. Accordingly, LCDs control light transmittance characteristics of liquid crystal material using electric fields applied between pixel and common electrodes in accordance with pixel voltage signals specific to a liquid crystal cell.
Data and gate drivers are directly connected to the liquid crystal display panel and are provided as a plurality of integrated circuits (ICs). Each of the gate driver ICs and data driver ICs are mounted to the liquid crystal display panel using tape carrier package (TCP) or chip on glass (COG) techniques. Further TCP-type gate and data driver ICs are connected to the liquid crystal display panel via a tape automated bonding (TAB) technique.
TCP-type gate and data driver ICs, connected to the liquid crystal display panel by the TAB technique, receive control signals and direct current (DC) voltage signals transmitted over signal lines provided on a printed circuit board (PCB). For example, data driver ICs are connected to each other in series, via signal lines mounted on a data PCB, receive control signals from the timing controller, and receive pixel data signals and driving voltages from the power supply. Gate driver ICs are connected to each other in series, via signal lines mounted on a gate PCB, receive control signals from the timing controller, and receive driving voltages from the power supply.
COG-type gate and data driver ICs are connected to each other via signal lines formed using a line-on-glass (LOG) technique. Mounted on a lower glass substrate of the liquid crystal display panel, the signal lines formed using the LOG technique receive control signals from the timing controller and power supply and driving voltages from the power supply.
Even when the various driver ICs are connected to liquid crystal display panels via the TAB technique, the LOG technique is typically adopted to eliminate the PCB and provide a thinner overall liquid crystal display. For example, signal lines connecting the gate driver ICs are relatively small and are provided directly on the liquid crystal display panel. Accordingly, gate driver ICs are connected to the liquid crystal display via the TAB technique, connected to each other in series via signal lines mounted on a lower glass substrate of the liquid crystal display panel, and receive control and driving voltage signals (i.e., gate driving signals).
Referring to FIG. 1, liquid crystal displays including LOG signal lines (e.g., formed without the gate PCB) typically include a liquid crystal display panel 1, a plurality of data TCPs 8 connected between a first side of the liquid crystal display panel 1 and a data PCB 12, a plurality of gate TCPs connected to a second side of the liquid crystal display panel 1, data driver ICs 10 mounted on the data TCPs 8, and gate driver ICs 16 mounted on the gate TCPs 14.
The liquid crystal display panel 1 includes a lower substrate 2 supporting signal lines and a thin film transistor array, an upper substrate 4 supporting a color filter array, and a layer liquid crystal material injected between the lower and upper substrates 2 and 4, respectively. The liquid crystal display panel 1 further includes a picture display area 21 having liquid crystal cells arranged where gate lines 20 and data lines 18 cross each other. The data driver ICs 10 convert digital pixel data signals into analog pixel voltage signals and apply the analog pixel voltage signals to the data lines 18.
Data pads and gate pads (not shown) are arranged at respective ends of the data and gate lines 18 and 20 at an outer portion of the lower substrate 2, outside the picture display area 21. An LOG signal line group 26 is positioned within the outer area and transmits gate driving signals to the gate driver ICs 16.
Data TCPs 8 include input pads 24 and output pads 25 for electrically connecting the data driver IC 10 mounted thereon to the data PCB 12 and the data lines 18. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12 while the output pads 25 of the data TCP 8 are electrically connected to the data pads arranged on the lower substrate 2. A first data TCP 8 is further provided with a gate driving signal transmission group 22. The gate driving signal transmission group 22 electrically connects the LOG signal line group 26 to the timing controller and power supply via the data PCB 12.
Each of the gate TCPs 14 includes a gate driving signal transmission line group 28 and output pads 30 electrically connecting the gate driver ICs 16 mounted thereon to the LOG signal line group 26 and the gate lines 20, respectively. Accordingly, the output pads 30 are electrically connected to the gate pads arranged on the lower substrate 2.
Each gate driver IC 16 sequentially applies a scanning signal (e.g., a gate high voltage signal (Vgh)) to each of the gate lines 20 in response to inputted control signals. Further, the gate driver ICs 16 apply a gate low voltage signal (Vgl) to each of the gate lines 20 that do not receive the gate high voltage signal (Vgh).
The LOG signal line group 26 typically consists of signal transmission lines and transmits direct current (DC) voltage signals (e.g., gate high voltage (Vgh), gate low voltage (Vgl), common voltage (Vcom), ground voltage (GND), supply voltage (Vcc) signals, etc.) and gate control signals (e.g., gate start pulse (GSP), gate shift clock (GSC), gate enable (GOE) signals, etc.).
Referring now to FIG. 2, individual signal transmission lines within the LOG signal line group 26 are arranged in a fine parallel pattern and are provided within a narrow space, similar to a space where signal lines in gate and data pads are positioned at outer portions of the picture display area 21. Signal transmission lines within the LOG signal line group 26 are formed of the same metal as the gate metal layer and are arranged on the lower substrate 2. Gate insulating and protective films 34 and 36, respectively, are disposed over the LOG signal line group 26. Being formed from the same material as the gate metal, signal transmission lines within the LOG signal line group 26 typically have a resistivity of 0.046 and are formed simultaneously with the gate lines 20. Thus, the LOG signal line group 26 has a larger resistance than signal lines, typically made of a material such as copper, formed in the gate PCB. As resistance values of signal transmission lines within the LOG signal line group 26 are proportional to their lengths, the resistance of signal transmission lines increases as the distance from the data PCB 12 increases. Accordingly, gate driving signals, transmitted via the LOG signal line group 26, become attenuated, their voltage values become distorted, and the quality of pictures capable of being displayed on the liquid crystal display becomes deteriorated.
For example, distortion of the gate low voltage signal (Vgl) transmitted through the LOG signal line group 26 affects the picture quality displayed within the picture display area 21. Gate low voltage signals (Vgl) maintain the pixel voltage charged within the liquid crystal cell between intervals when the gate high voltage (Vgh) is charged within the pixel. Accordingly, as the gate low voltage signal is distorted, the pixel voltage within the liquid crystal cell becomes distorted.
Referring still to FIG. 2, LOG gate low voltage transmission lines VGLL, arranged within the LOG signal line group 26, supply the gate low voltage (Vgl) and include first to fourth LOG gate low voltage transmission lines VGLL1 to VGLL4. The first to fourth LOG gate low voltage transmission lines VGLL1 to VGLL4 electrically connect the first data TCP 8 and first to fourth gate TCPs 14A to 14D, respectively. The first to fourth LOG-type gate low voltage transmission lines VGLL1 to VGLL4 have intrinsic line resistance values a, b, c, and d, proportional to their lengths, and are connected to each other in series via the first to fourth gate TCPs 14A to 14D.
The line resistance values a, b, c, and d alter the gate low voltages (Vgl) supplied to each gate driver IC 16. For example, the first gate driver IC 16, mounted on the first gate TCP 14A, is supplied with a first gate low voltage (VGL1). The voltage value drop of the first gate low voltage (VGL1) is proportional to the first line resistance value a of the first LOG gate low voltage transmission line (VGLL1). The first gate low voltage (VGL1) is applied to gate lines at a first horizontal line block A via the first gate driver IC 16.
The second gate driver IC 16, mounted on the second gate TCP 14B, is supplied with a second gate low voltage (VGL2). The voltage value drop of the second gate low voltage (VGL2) is proportional to the first and second line resistance values of the first and second LOG gate low voltage transmission lines (VGLL1 and VGLL2) connected to each other in series, a+b. The second gate low voltage (VGL2) is applied to gate lines at a second horizontal line block B via the second gate driver IC 16.
The third gate driver IC 16, mounted on the third gate TCP 14C, is supplied with a third gate low voltage (VGL3). The voltage value drop of the third gate low voltage (VGL3) is proportional to the first, second, and third line resistance values of the first to third LOG gate low voltage transmission lines (VGLL1 to VGLL3) connected to each other in series, a+b+c. The third gate low voltage (VGL3) is applied to gate lines at a third horizontal line block C via the third gate driver IC 16.
The fourth gate driver IC 16, mounted on the fourth gate TCP 14D, is supplied with a fourth gate low voltage (VGL4). The voltage value drop of the fourth gate low voltage (VGL4) is proportional to the first to fourth line resistance values of the first to fourth LOG gate low voltage transmission lines (VGLL1 to VGLL4) connected to each other in series, a+b+c+d. The fourth gate low voltage (VGL4) is applied to gate lines at a fourth horizontal line block D via the fourth gate driver IC 16.
As differences between the gate low voltages VGL1 to VGL4 applied to the gate lines via each gate driver IC 16 occur, the brightness to which images are displayed across the horizontal line blocks A to D becomes non-uniform. The non-uniform brightness across horizontal line blocks A to D induces a cross-line phenomenon (32) that divides the screen in brightness values and thereby deteriorates the picture quality of the liquid crystal display. Between the first gate driver IC 16 and the fourth gate driver IC 16, first to fourth line resistance values a, b, c, and d are added to each other. Accordingly, the first gate low voltage (VGL1) is greater than the second gate low voltage (VGL2), the second gate low voltage (VGL2) is greater than the third gate low voltage (VGL3), and the third gate low voltage (VGL3) is greater than the fourth gate low voltage (VGL4).
For each of the gate driver ICs 16, gate low voltage differences such as those described above can be compensated for by providing a plurality of LOG gate low voltage transmission lines independently connected to their corresponding gate driver ICs 16 and/or by enlarging the cross-sectional area of the signal transmission lines. However, these compensation solutions are difficult to satisfactorily achieve because the area in which the LOG signal line group 26 is located is not expandable and providing independently connected LOG gate low voltage transmission lines with enlarged cross-sectional areas within such small, confined spaces is difficult.
Accordingly, gate low voltage differences caused by the line resistance must be compensated for without altering the design of the LOG gate low voltage line VGLL.